1. Field of the Invention
The present disclosure generally relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming FinFET devices in different regions of an integrated circuit product, such as the memory and logic regions of an integrated circuit product.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. Trenches T are formed in the substrate B to define the fins C. The gate structure D is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. The 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the sub-20 nm CMOS technology node and beyond.
Both FET and FinFET semiconductor devices have an isolation structure, e.g., a shallow trench isolation structure, that is formed in the semiconducting substrate around the device so as to electrically isolate the semiconductor device. Traditionally, isolation structures were always the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the semiconductor device. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching the trenches in the substrate that defined the fins. As FinFET devices have been scaled to meet ever increasing performance and size requirements, the width W of the fins C has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm.
However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form the trenches T in the substrate B to define multiple “fins” that extend across the substrate, and thereafter remove some of the fins C where larger isolation structures will be formed. Some of the fins (or portions thereof) will be “active fins,” i.e., fins that are part of a functional FinFET device, while some of the fins (or portions thereof) are sacrificial or “dummy fins” that will be removed after all of the fins are initially formed. The fins will also be cut—an end cut process—to their desired final axial length. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins C to very small dimensions due to the more uniform environment in which the etching process that forms the trenches T is performed. As noted above, after the trenches T have been formed, some of the fins C must be removed to remove sacrificial fins and/or to create room for or define the spaces where isolation regions will ultimately be formed. There are two commonly employed techniques for accomplishing the goal of removing the desired number of fins C: (1) “Fins-cut-First” and (2) “Fins-cut-Last,” etc.
Semiconductor memory devices are in widespread use in many modern integrated circuit devices and in many consumer products. In general, memory devices are the means by which electrical information is stored. There are many types of memory devices, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), ROMs (Read Only Memory), etc., each of which has its own advantages and disadvantages relative to other types of memory devices. For example, SRAMs are typically employed in applications where higher speed and/or reduced power consumption is important, e.g., cache memory of a microprocessor, mobile phones and other mobile consumer products, etc. Millions of such memory devices are typically included in even very basic electronic consumer products. Irrespective of the type of memory device, there is a constant drive in the industry to increase the performance and durability of such memory devices. In typical operations, an electrical charge (HIGH) is stored in the memory device to represent a digital “1”, while the absence of such an electrical charge or a relatively low charge (LOW) stored in the device indicates a digital “0”. Special read/write circuitry is used to access the memory device to store digital information on such a memory device and to determine whether or not a charge is presently stored in the memory device. These program/erase cycles (“P/E cycles”) typically occur millions of times for a single memory device over its effective lifetime.
In general, efforts have been made to reduce the physical size of such memory devices, particularly reducing the physical size of components of the memory devices, such as transistors, to increase the density of memory devices, thereby increasing performance and decreasing the costs of the integrated circuits incorporating such memory devices. Increases in the density of the memory devices may be accomplished by forming smaller structures within the memory device and by reducing the separation between the memory devices and/or between the structures that make up the memory device. Often, these smaller design rules are accompanied by layout, design and architectural modifications which are either made possible by the reduced sizes of the memory device or its components, or such modifications are necessary to maintain performance when such smaller design rules are implemented.
Many different types of devices, having different configurations, are typically formed on the same integrated circuit product. For example, memory devices, such as SRAMs, and logic devices, such as microprocessors, are typically part of the same integrated circuit product. As is common, the substrate is segregated into different areas or regions where these different devices are formed. As an example, the substrate may be segregated into one or more logic areas, where logic devices are formed, and one or more memory areas, where memory devices are formed. Unfortunately, when the memory devices and logic devices are made using FinFET devices, the fin removal process discussed above may be more problematic due to the more complicated arrangement of the active and dummy fins in memory devices, such as SRAM devices, as compared to the arrangement of active and dummy fins in logic devices. For example, in SRAM devices, a single dummy fin that is positioned next to a single active fin must be removed without damaging the single active fin. Such a situation is typically not present in many logic devices. Similar problems may arise when forming two different types of logic devices, e.g., standard logic devices and non-standard (analog) logic devices.
FIG. 2 is a simplistic depiction of an illustrative logic area 20 of an integrated circuit product that includes a plurality of fins, generally designated with the reference number 22, that are formed in a substrate. The fins 22 are initially formed as a so-called “sea-of-fins” across the entire substrate. The fins 22 include active fins 22A and sacrificial fins 22R that will eventually be removed (different shading has been used for each type of fin). Also depicted in dashed lines are illustrative gate structures 24 that will eventually be formed across the active fins 22A after the sacrificial fins 22R are removed. Given the regular arrangement of the fins 22 in the logic area 20, the fin removal process is relatively straightforward.
FIGS. 3A-3B are simplistic depictions of two different versions of SRAM devices wherein both active fins 22A and sacrificial fins 22R have been formed above the substrate as part of the formation of the initial “sea-of-fins.” Also depicted are illustrative active regions 26, gate structures 24 (dashed lines) that will eventually be formed on the device, as well as an identification of the pull-up transistor (PU), the pull-down transistor (PD) and the pass gate transistor (PG) of the devices. FIG. 3A depicts a dense SRAM 30 wherein the pull-down transistor and the pass gate transistor only have a single active fin 22A. FIG. 3B depicts another SRAM 40 wherein the pull-down transistor and the pass gate transistor each have two active fins 22A. As noted above, the sacrificial fins 22R will need to be removed at some point in the process flow. One problem is that the spacing 23 is smaller than the pitch between adjacent fins in logic devices. With such tight pitches in the SRAM devices, the traditional fin removal processes mentioned above may tend to damage adjacent active fins in the SRAM devices.
The present disclosure is directed to various methods of forming FinFET devices in different regions of an integrated circuit product that may avoid, or at least reduce, the effects of one or more of the problems identified above.